Question: Question 1 : Loop unrolling and Static Multi - issue ( 2 5 points ) Assume that you are given a dual - issue pipeline

Question 1: Loop unrolling and Static Multi-issue (25 points)
Assume that you are given a dual-issue pipeline for RISC-V ISA. You can schedule ALU or branch instruction in the first issue slot, and load/store instruction in the second issue slot of the issue package. You are given the following sequence of instructions.
Loop:
\table[[lw,x7,0(x10),#read from memory],[add,x7, x7, x11,#update value],[sw,x7,0(x10),#store it back to memory],[addi,x10, x10,0x4,#update the address],[bne,x10, x12, Loop,#Loop until the address is not equal to the content of x12]]
a)[10 points] Assume that the loop index for the given loop above is divisible by 3. Unroll the given loop 3 times. Use register renaming as necessary to avoid any name dependencies.
b)[10 points] How would the unrolled loop in (a) be scheduled on the given static dual-issue pipeline? You may use the following template to show the schedule.
\table[[,\table[[1st Slot],[(ALU or branch)]],\table[[2nd Slot],[(load or store)]]],[Package 1,,],[Package 2,,],[Package 3,,],[Package 4,,],[Package 5,,],[Package 6,,]]
c)[5 points] Calculate and report the IPC of the system after the loop unrolling, separately. How much speedup achieved after loop unrolling?
 Question 1: Loop unrolling and Static Multi-issue (25 points) Assume that

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