Question $1$

The block diagram for a RF transceiver IC is shown in Figure $1$ below. It is capable of simultaneous transmission and reception although they may be time multiplexed if desired. There are two receiver path, denoted $"$Rx A$"$ and $"$Rx B$"$ making it suitable to diversity $/$ multi$-$antenna applications, e$.$g$.$ WiFi.

Figure $1$: A block diagram of the MAX$2839$ RF transceiver to be considered in question $1.$

$1\mathrm{.}1$ What kind of receiver architecture is being used here? Provide reasons for your decision and explain why the designers did not include a filter before the mixers, hence or otherwise indicate how the image frequency problem is be avoided in this architecture.

$1\mathrm{.}2$ Provide details of what processing blocks might appear after each of the receivers, i$.$e$.$ connected to the Rx A and B outputs.

$1\mathrm{.}3$ There are RSSI blocks $($Received Signal Strength Indication$)$ that can measure the signal strengths at an internal point in both receivers. What is the purpose $/$ need for this capability.

$1\mathrm{.}4$ The I$/$Q gain and phase imbalance of the receiver mixers are specified as being $0\mathrm{.}1$ dB and $\backslash (0\mathrm{.}125^\{\backslash$circ$\}\backslash )$ respectively. What is the importance of this specification on the receiver's performance.

$1\mathrm{.}5$ The PLL is actually a fractional$-$N PLL$,$ having an external Crystal $("$XTAL$1")$ as a reference and some external components labelled $"$PLL filter". Why are these components external to the chip and what determines the minimum and maximum frequencies that can be provided to the mixing circuits?