Question: Consider the following code: module FF (Q, X, Clk, rst); output Q; input X, Clk, rst; reg Q; always @ (posedge CLK, negedge rst)

Consider the following code: module FF (Q, X, Clk, rst); output Q; input X, Clk, rst; reg Q; always @ (posedge CLK, negedge rst)

Consider the following code: module FF (Q, X, Clk, rst); output Q; input X, Clk, rst; reg Q; always @ (posedge CLK, negedge rst) if (rst = 0) Q In Verilog, a module cannot be nested, but a (case) can. Select one: O True O False

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