Consider the following code fragment:
if K > 10
L: = K + 1
else
L: = K - 1;
A straightforward translation of this statement into SPARC assembler could take the following form:

The code contains a nop after each branch instruction to permit delayed branch operation.
a. Standard compiler optimizations that have nothing to do with RISC machines are generally effective in being able to perform two transformations on the foregoing code. Notice that two of the loads are unnecessary and that the two stores can be merged if the store is moved to a different place in the code. Show the program after making these two changes.
b. It is now possible to perform some optimizations peculiar to SPARC. The nop after the ble can be replaced by moving another instruction into that delay slot and setting the annul bit on the ble instruction (expressed as ble,a L1). Show the program after this change.
c. There are now two unnecessary instructions. Remove these and show the resulting program.

sethi %hi(K), %r8 [%r8 + % lo(K)], % r8 %r8, 10 L1 load high-order 22 bits of address of location K into register r8 ;load contents of location K into r8 compare contents of r8 with 10 branch if (r8) s 10 ld cmp ble nop sethi ld inc sethi st b nop sethi ld dec sethi st %hi(K), % [%r9 + %lo(K)], %r9 % %hi(L), %r10 9ers, 1%r10 + % lo(L)] L2 ;load contents of location K into r9 add1 to (r9) store (r9) into location L LI: %hi(K), %r11 [%r11 + %lo(K)], %r12 96T12 %hi(L), %r13 %r12. [%r13 + %lo(L)] ;load contents of location K into r12 subtract1 from (r12) store (r12) into location L L2: