Question 19 In verilog, a binary bit having values not equal to 0 or 1 is...

Transcribed Image Text:

Question 19 In verilog, a binary bit having values not equal to 0 or 1 is considered wrong. Not yet answered Select one: O True Marked out of 1.00 False P Flag question Question 18 In Verilog, a module cannot be nested, but a (case) can. Not yet answered Select one: Marked out of O True 1.00 False P Flag question Question 19 In verilog, a binary bit having values not equal to 0 or 1 is considered wrong. Not yet answered Select one: O True Marked out of 1.00 False P Flag question Question 18 In Verilog, a module cannot be nested, but a (case) can. Not yet answered Select one: Marked out of O True 1.00 False P Flag question