Question: Question 2 0 / 1 pts If it takes 1 bus cycle to transmit 1 word between the L2 cache and memory, and 18 bus

Question 2 0 / 1 pts If it takes 1 bus cycle to transmit 1 word between the L2 cache and memory, and

Question 2 0 / 1 pts If it takes 1 bus cycle to transmit 1 word between the L2 cache and memory, and 18 bus cycles to find each word in memory. What is the miss penalty in the L2 cache with 4-word blocks in bus cycles (assume 32-bit addresses)

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