Question 2 (10 Marks) a) Assume there are three small caches, each consisting of four one-word blocks and uses LRU replacement policy. One cache is fully associative, a second is two-way set- associative, and the third is direct mapped. Find the number of misses for each cache organization given the following two independent sequences of block addresses: 0,2,4,8,10,12,14,16,0 1,3,5,1,3,1,3,5,3 15 Marks) d) Suppose we have a processor with a base of 1.1, assuming all references hit in the primary cache, and a clock rate of 3GHz. Assume a main memory access time of 200ns including all the miss handling. Suppose miss rate per instruction at the primary cache is 2%. How much faster will the processor be if we add a secondary cache that has 2ns access time for either a hit or a miss and is large enough to reduce the miss rate to main memory to 1%. 15 Marks