Question 2: [12] You are given the following data items, which are requested by the processor. You need to simulate FIFO and LRU caching mechanisms, for a cache size of 3. You need to show the items in the cache after every data access. Additionally, you need to show which data items are Hit and which are Miss. Additionally, you need to show how many hits and how many misses have occurred a. Simulation with FIFO. Show cache items after every data access. Show which data items are hit and which are miss. Show how many hits and how many misses have occurred. [6] b. Simulation with LRU. Show cache items after every data access. Show which data items are hit and which are miss. Show how many hits and how many misses have occurred. [6] Data items access: 1 2 3 1 4 1 2 2