QUESTION $22$

Suppose you have a system with the following:

an $L1$ cache that has a hit time of $2$ cycles and a miss rate of $20\%$

main memory with access time of $100$ cycles What is the AMAT $($Average Memory Access Tim$)$ of the system?

a$.2$ cycles

b$.10$ cycles

c$.22$ cycles

d$.51$ cycles

QUESTION $5$

What would be the value of the output $Y$ for the circuit shown in Figure $4$ if the inputs are $A=0,B=1,C=0?$

a$.$ undefined

b$.0$

C$.1$

d$.$ Either $0$ or $1,$ depending on the clock