Question $2(35$ points$)$:

A Pipelined Processor has a base CPI of $1.$ The processor also has a $L1$ cache. The penalty for a

branch mispredict is $3$ cycles and the penalty for accessing main memory is $100$ cycles. The

branch predictor is $90\%$ accurate, $L1$ has a local miss rate of $3\%,10\%$ of instructions are

memory instructions, $15\%$ of instructions are branches, and $25\%$ of instructions require $1$ stall

due to data hazards.

A$)(10$ Points$)$ What is the CPI increase for branch penalties?

Name:

B$)(10$ Points$)$ What is the CPI increase for memory instructions causing the program to stall?

C$)(10$ Points$)$ What is the CPI increase for data hazards causing the program to stall?

D$)(5$ Points$)$ What is the speedup of the processor if the branch predictor was perfect $(0\%$

mispredicts$)$ and the cache was perfect $(0\%$ miss rate on $L1).$