QUESTION $2][40$ points$]$ A memory sub$-$system will be designed for a $8086-$based sytem. TWO $64$Kx$8$ BIT E PROM chips and four $32$Kx$8$ bit RAM chips will be used.Suppose CHip select inputs of all memory chips are active high a$)(5$ points$]$ Calculate overall total memory capocity $($as $KB)$ that will be used. Calcutate how mamy address lines $($at minimum$)$ in Address Bus should be used for location selection for each chip types. Calculate how many address lines $($at minimum$)$ should be used for chlip selections. b$)[20$ points$)$ Draw the schematic diagram that shows Address Decoding circuit for memory chips $($odd banks and even banks$),$ Use an appropriate Acidress Decoder chip for memory chip selections, Show address bus, data bus, and chip select connections to all memory chiph. c$)[8$ points$]$ For each memory chips $($odd banks and even banks$),$ write the address map table containing only the smallest addresses $($in binary notation and abe in hexadecimal notation.$)$

d$)[7$ points$]$ By using the addiress map found in question$-$c$,$ for each memory chips, write the address map table containing only the bigets addresses $($in binary notation and also in heradecimal notation.$)$