Question: Question 2. Answer the below questions for the Verilog code given below. (24 points, 4 points each) 1 module ECET146 (clk, reset, out); 2 input

Question 2. Answer the below questions for the Verilog code given below. (24 points, 4 points each) 1 module ECET146 (clk, reset, out); 2 input clk, reset; 3 output [2:0] out; 4 reg [2:0] temp = 3'b111; 5 6 always @(negedge clk, posedge reset) 7 begin 8 if (reset) 9 temp

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