Question #2: CLO 3 (Marks: 25) 3. Assume a processor has data cache and instruction cache each of 32 KB, with 16-word blocks. System has single RAM chip of 4GB. If both caches using direct mapped algorithm for mapping then a) Memory address will be didvided into how many fields and what are bits dedicated to each field b) Cacluate size of one entry in cache c) If instruction miss rate is 0.5% and data miss rate is 2.3%. Assume a processor has a CPI of 2.5 without any memory stalls and the miss penalty is 70 cycles for all misses, determine how much faster a processor would run with a perfect cache that never missed. Assume the frequency of all data access in memory is 25%. O