Question 2. Indirect Addressing Load Cycle [ 3 marks ] The timing cycle for the Load Accumulator (LDA) instruction, using indirect access to memory M is provided below. The notation used is the same as in the lecture notes. Note that the register transfer language and microoperations listed are also consistent with Mano's notation. T2: D7,D6., DD DEC(IR(12-14)), I-IR(15), AR I D2 T3 DR M[AR], SC-SC+1 I D2 T4 : AR-DR(0-1 l), SC-SC + I IR(, SC-SC+1 The registers PC, AR, IR, DR, SC and AC are the same as defined by Mano (and lecture notes), while the I and DECoder outputs Dx and timing decoder outputs Tx are also the same as defined by Mano. Based on the block diagram for Question 1 above, draw a block diagram for the different aspects of this circuit that perform the extra memory fetch and indicate whether there should be any changes to the direct addressing LDA. Also, show how the various connections must be made of the indirect addressing mode of the LDA instruction. Question 2. Indirect Addressing Load Cycle [ 3 marks ] The timing cycle for the Load Accumulator (LDA) instruction, using indirect access to memory M is provided below. The notation used is the same as in the lecture notes. Note that the register transfer language and microoperations listed are also consistent with Mano's notation. T2: D7,D6., DD DEC(IR(12-14)), I-IR(15), AR I D2 T3 DR M[AR], SC-SC+1 I D2 T4 : AR-DR(0-1 l), SC-SC + I IR(, SC-SC+1 The registers PC, AR, IR, DR, SC and AC are the same as defined by Mano (and lecture notes), while the I and DECoder outputs Dx and timing decoder outputs Tx are also the same as defined by Mano. Based on the block diagram for Question 1 above, draw a block diagram for the different aspects of this circuit that perform the extra memory fetch and indicate whether there should be any changes to the direct addressing LDA. Also, show how the various connections must be made of the indirect addressing mode of the LDA instruction