Question: Question 3 ( a ) The STM 3 2 L 0 3 1 s CPU core is an Arm Cortex M 0 + . It

Question 3
(a) The STM32L031s CPU core is an Arm Cortex M0+. It does not allow data
transfers directly from one memory location to another. If a symbol X is declared as shown below, write the Arm-Thumb (assembler) instructions necessary to read the val ue stored at X into register R0
AREA DATA
X DCD 10
[4 marks]
(b) The MOVS instruction provides an efficient way of loading a limited range of
values into a Cortex M0+ register. What range of values is allowed?
[2 marks]

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