Question 3 Complete the design for the fundamental mode circuit represented by the timing diagram of figure Q3. a) Obtain the primitive flow map. [10] b) Find all pairs of equivalent or compatible states using an implication chart. [15] c) Determine the minimum number of states for the design using a merger diagram. [10] d) Obtain a reduced flow map using a minimum set of mergeable states, and assign a single state name to each group of merged states. [6] e) Obtain a composite Karnaugh map with a race-free assignment. Hence determine logic hazard-free equations for the circuit and draw a gate-level circuit implementation. [10] IX Input Input X2 Output Z Figure Q3 Question 3 Complete the design for the fundamental mode circuit represented by the timing diagram of figure Q3. a) Obtain the primitive flow map. [10] b) Find all pairs of equivalent or compatible states using an implication chart. [15] c) Determine the minimum number of states for the design using a merger diagram. [10] d) Obtain a reduced flow map using a minimum set of mergeable states, and assign a single state name to each group of merged states. [6] e) Obtain a composite Karnaugh map with a race-free assignment. Hence determine logic hazard-free equations for the circuit and draw a gate-level circuit implementation. [10] IX Input Input X2 Output Z Figure Q3