Question 3. Draw the datapath structure defined as follows. An 8-bit register with output d out is to be reset to a value of 8hff on an active high synchronous reset. If not being reset, the register shall clear to a value of 8h00 if an active low clear n signal is asserted. If neither reset nor clear n is asserted, the d out output shall take on the value of the d in input if the active high enable signal is asserted. If no controlling signals are asserted then the output shall remain unchanged.

Figure 3.1: Block Diagram