Question 3 (Marks: 10 = 4*2.5) Question 10.0 points possible (graded, results hidden) Assume a pipelined processor with five pipeline stages where each stage takes one clock cycle. Further, assume that the processor has to execute the following instruction sequence ADD $TO, $T1, $T3 ADDI $51, $S1, 4 LW $50, ($51) SUB $55, $50, $TO AND $T3, T4, $55 SW $55, ($51) MULT $52, $56, $T3 SUB $T6, $T7, $56 How many stalls (in terms of the number of stall clock cycles) will the processor experience if it does not have any forwarding unit to reduce or eliminate pipeline stalls? (Assume that the write back step of an earlier instruction and the instruction decode step of a subsequent dependent instruction can happen in the same clock cycle)