Question 3: Provide solution for Question 3 and explain reasoning in detail- Here is the following truth table ABC| F 0 01 1 0 10 10 1 a) b) c) Implement the function F by using a multiplexer 8 to 1 Draw the circuit implementing the function F in form of a "Black Box"- meaning, identify the inputs and the outputs and the box representing the circuit's functionality Code a VHDL module of the behavioral style implementing the function defined by the truth table d) Suppose that the VHDL implementation of the module MUX8 (a multiplexer 8 to 1) is provided library IEEE use IEEE. STD LOGIC 1164.all; entity mux8 is port (do, di, d2, d3, d4, d5, d6, d7 in STD LOGIC y t STD LOGIC) end; Write the VHDL module moduleF of the structural style implementing the function F defined by the truth table presented earlier and implemented using a MUX8. (Give your solution of 3(b) but in VHDL of the structural style)