Question $3$

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Assume that you wrote a conditional operator to create a MUX$2$ in your Verilog design. However, upon looking at the synthesized netlist, you see that your MUX$2$ was optimized into an AND$2$ gate.

a$.$ Give a line of Verilog with a conditional operator that will be optimized into an AND$2$ gate.

b$.$ Assume somewhere else in your design, a MUX$2$ was optimized into a NOT gate. Give a line of Verilog with a conditional operator that will be optimized into an NOT gate.

c$.$ Assume somewhere else in your design, a MUX$2$ was optimized into an OR$2$ gate. Give a line of Verilog with a conditional operator that will be optimized into an OR$2$ gate.