Question 4 (10 marks) Datapath below shows a pipelined MIPS implementation. Given registers $1 = 4. $2 = 8. $3 = 12. $4 = 16. $5 = 20, $6 = 24, $10 = 28, $11 =32, $12 = 36, $13 = 40 and $14 = 44, and memory locations [24] = 50 and [28] = 100, what are sizes and values of the data in the indicated locations? If any value is unknown, put an "X". Size (or Number of bits) Value A B C D E F G H I J add $14, $5, $6 Instruction fetch lw $13.24 ($1) Instruction decode add $12, $3, $4 Execution sub $11, $2, $3 Memory lw $10, 20(81) Write-back IF/D ID/EX EX/MEM MEMWB Add Ada 40 Shirt left 2 B PC ASS Road register 1 ruction Food data 1 1 Zero Instruction memory Registers Read ALU ALU Read rogister Write rogistor rest Address write Data memory 2 white 18 Sign extend H Question 5 (10 marks) The pipelined MIPS implementation in Question 4 can be modified to resolve data hazards through Forwarding. Draw a possible internal circuit diagram of the Forwarding Unit shown in the datapath below. ID/EX WB EX/MEM Control M WB MEM/WB WBI IF/ID EX M 0 1 Instruction Registers ALU M PC Instruction memory Ex- Data memory IF/ID. RegisterRs IF/ID. RegisterRt IF/ID. RegisterRt IF/ID. RegisterRd Rs RI Rt Rd EX/MEM.RegisterRd Forwarding unit MEMWB. RegisterRd Question 6 (10 marks) Consider the same datapath in Question 5, how can the register file be modified to resolve the data dependence between the first and fourth instructions in the following program? To demonstrate this modification, design a register file containing four two-bit registers. Time (in clock cycles) Value of CC 1 CC 2 CC 3 CC 4 CC 5 CC 6 CC 7 CC 8 CC 9 register $2: 10 10 10 101-20 -20 -20 -20 -20 10 Program execution order (in instructions) sub $2, $1, $3 IM DM Reg and $12, $2, $5 IM Reg DM or $13, $6, $2 IM Freg DM add $14, $2,$2 IM Regl DM Regi sw $15, 100($2) IM Reg DM Reg