Question $4(30$ points$).$ A MIPS assembly code is shown below. The assembly code is executed

using a $5-$stage MIPS processor and we can actually decide the branch a little earlier, in ID instead

of EX$.$ Answer the following questions:

Loop: sub $$19,$ $$19,$ $$20$

addi $$9,$ $$20,5$

sw $$9,0($$$21)$

addi $$10,$$$19,2$

sll $$10,$ $$10,$ $$3$

add $$10,$ $$10,$ $$21$

addi $$11,$ $$20,1$

sll $$11,$ $$11,3$

add $$11,$ $$11,$ $$21$

lw $$11,0($$$11)$

sub $$9,$ $$9,$ $$11$

sw $$9,0($$$10)$

beq $$9,$ $$0,$ Loop

addi $$9,$ $$12,2$

a$).$ Identify all the stalls $($which two instructions or which register are the cause of the stall$)$ and the total

number of stalls in the above assembly code. Assume there is no forwarding, no branch prediction, and

no duplicate copies of instruction memory or data memory.

b$).$ Reorder the above code to reduce the stalls $($get the smallest number of stalls$)$ without changing the

functionality. Assume there is no forwarding, no branch prediction, and no duplicate copies of instruction

memory or data memory. Identify all the stalls $($which two instructions or which register are the cause of

the stall$)$ and the total number of stalls in the reordered assembly code.

c$).$ Reorder the above code to reduce the stalls without changing the functionality $($get the smallest

number of stalls$).$ Assume there is forwarding, no branch prediction, and no duplicate copies of

instruction memory or data memory. Identify all the stalls $($which two instructions or which register are

the cause of the stall$)$ and the total number of stalls in the reordered assembly code.

d$).$ Based on c$),$ plot the pipeline diagram to show the execution of these instructions and clearly

show the data forwarding$/$bypassing in the pipeline diagram. $[$hint: The instruction sequence is shown

vertically, from top to bottom. Clock cycles are shown horizontally, from left to right. Each instruction is

divided into its component stages.$].$ Question $3(20$ points$).$ Assuming the following functional unit latencies:

$.$ What is the cycle time of a single$-$cycle implementation? What is the cycle time of a pipelined

implementation?

Given the program below:

lw a$2)$

subi $t$0,$ $t$1,1$

addi $v$0,$$$0,0$

add $t$0,$$$0,$$$0$

add $t$4,$ $a$0,$ $a$1$

$.$ The assembly code is executed using a $5-$stage MIPS processor. Plot the pipeline diagram to

show the execution of these five instructions. $[$hint: The instruction sequence is shown vertically, from

top to bottom. Clock cycles are shown horizontally, from left to right. Each instruction is divided into its

component stages.$].$

$.$ If the given program is run on the single$-$cycle implementation, how many cycle does it take to

execute these five instructions? How long does it take to complete execution $($ns$)?$

$.$ If the given program is run on the pipelined implementation, how many cycles does it take to

execute these five instructions? How long does it take to complete execution $($ns$)?$Question $2(10$ points$).$ Given the program below,

li $t$1,0$

li $t$2,10$

beq $t1,$t$2,$ Exit

addi $t1,$t$1,1$

j L

Exit:

$.$ How many static instructions in the program? How many dynamic instructions in the program?

$["$Exit$"$ is a label not an instruction$]$

$.$ Compare the performance of the following two processors:

P$1$: $1$ GHz $,$ with a CPI of $1\mathrm{.}2$ for the given program

P$2$: $2$ GHz $,$ with a CPI of $1$ for the same program

Calculate the CPU execution time of these two processors on the given program. Which processor is

faster in executing the given program? How much faster?