Question $4(3$ marks$)$

usio all sol megaib sigolo

Use the following Verilog module to answer the question below.

module my$\_$unit $($clk$,$ x$,$ y$1,$ y$2)$;

input clk$,$ x;

output yl$,$ y$2$;

reg yl$,$ y$2$;

wire w;

assign w $=$ x$/(-$yl$)$;

always @$($posedge clk$)$

y$2<=$ w;

always @$($negedge clk$)$ yl $<=$ y$2$;

endmodule

$($a$)(1$ marks$)$ Draw the output waveforms for the specified inputs.

clk

X

yl

y$2.$

ham $($d$)$