Question 4. [5] In Figure 1, a sample port I/O bus architecture is shown, with the size of the address buses and data buses labelled. An 8-bit data bus denotes here a byte-addressable read/write cycle, while a 16-bit data bus denotes here a word-addressable read/write cycle, where a word here is 2 bytes in size. CPU memory address bus (16 bits) memory data bus (16 bits) Memory 1/0 data bus (8 bits) 1/0 address bus (16 bits) peripheral peripheral peripheral Figure 1: Port I/O sample bus structure (a)How many addressable locations are available for memory (a)How many addressable locations are available for memory? (b)What is the size of each location? (c)What is the maximum memory size in bytes? (c)What is the maximum memory size in bytes? (d)How large is the address space for I/O peripherals in bytes? (e)If every peripheral must be allocated an address space of 2 12 bytes, what is the largest number of peripherals that can be connected