Question $4)$ Suppose we are using a system employing Tomasulo's dynamic scheduling

algorithm. We have $3$ functional units with the following execution stage latencies:

In this question, assume that Tomasulo's algorithm satisfies the following conditions:

Each functional unit has one reservation station $($or store $/$ load buffer$)$

The execution stage of an instruction can begin after the issue stage

For example, if instruction $A$ is issued on $1$ cycle, it can begin its execution on cycle $2$

Reservation stations are deallocated during the write result stage and can be reassigned

on the following $($next$)$ cycle

For example, if a functional unit finishes the write result stage on cycle $10,$ it can issue

the next instruction on cycle $11$

Consider the following program:

At the start of the program, no register values are being computed by any functional units $($i$.$e$.,$ all

registers are "ready"$).$ Suppose the first instruction $($I$0)$ issues on cycle $1$ and start execution on

cycle $2.$ Answer the following questions.

Q$4-1)$ Which instructions are stalled in the issue stage?

Q$4-2)$ Which instructions are stalled in the execution stage?

Q$4-3)$ On which cycle does each instruction write back?