Question: Question 5 2 0 pts Clock 5 - Stage Pipeline System A computer pipeline has 5 stages and each stage has 9 0 PS processing

Question 5
20 pts
Clock
5-Stage Pipeline System
A computer pipeline has 5 stages and each stage has 90 PS processing time and 10 PS latching delay time.
Note 1GHz clock means 1000,000,000 clock cycles per second, each cycle is 1000 PS.
Answer the following 5 questions by filling the 5 blanks with numeric answers. If you answer has a fraction.enter only one digit of the fraction, i.e.33.333 should be entered as 33.3.
Total execution time for one instruction to complete through the 5-stage pipeline is PS.
Total execution time for one instruction to complete without a pipeline (1-stage processor) is PS.
Once the pipe is full, what is the throughput of the pipeline, meaning an instruction will complete every PS.
What is the 5-stage pipeline speedup over the 1-stage, that is Speedup =Tt=, where T is the execution time without the pipeline and t is the execution throughput with the pipeline.
What should be the maximum frequency of the pipeline clock if every stage takes one cycle GHz.
Question 5 2 0 pts Clock 5 - Stage Pipeline

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