Question: Question 5 Draw a circuit schematic for a D - flip - flop that is falling - edge - triggered and has a synchronous active

Question 5
Draw a circuit schematic for a D-flip-flop that is falling-edge-triggered and has a synchronous active-low reset. Use two latches and any additional required primitive gates.
Figure 1: D-Latch
Question 5 Draw a circuit schematic for a D -

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