Question $6.[16$ points$]$ Synchronous Sequential Circuits.

Design a serial data receiver$/$transmitter module. This module has two inputs: an externally driven

clock, and a single$-$bit signal: serial$\_$in$.$ It has one single$-$bit output signal serial$\_$out. Within the

module are two sub$-$modules: the receiver and the transmitter.

$($i$)$ Receiver: When no data is being transmitted to the receiver, the serial$\_$in signal is logic

HIGH. When the serial$\_$in signal is pulled to logic LOW, the roceiver reads the incoming

bit from serial$\_$in for the next $3$ clock cycles, allowing $3$ bits to be received by the receiver.

After reading $3$ bits, serial$\_$in returns to logic HIGH until the next sequence of $3$ bits is

transmitted. As soon as the serial$\_$in signal returns to logic HIGH, the receiver sends the

received $3-$bit data to the transmitter in parallel along with a single$-$bit "ready" flag. The

"ready" signal is initialized to logic LOW and changes to logic HIGH at the same clock

cycle as the receiver starts to transmit the $3-$bit data to the transmitter. The receiver then

waits for the transmitter to send a "done" flag, at which cycle it lowers "ready" again. The

receiver module is then ready for the next $3-$bit data transmission. You can assume that a

sufficient number of idle clock cycles are reserved before the next $3-$bit data is ready for the

receiver to read.

$($ii$)$ Transmitter: When the "ready" signal goes HIGH, the transmitter pulls serial$\_$out to

logic LOW to signal that it is about to transmit the received data from the receiver. Then

the transmitter spends the next $4$ clock cycles transmitting data on the serialout output:

It uses the first $3$ clock cycles to transmit the $3-$bit data $($one bit per cycle$)$ and uses the $4^("$th $")$

cycle to transmit a logic LOW. In the following clock cycle, the transmitter then issues the

"done" flag by setting it to logic HIGH. It then waits for the receiver to send the "ready"

signal.

$6$a$.(2$ points$)$ Draw a block diagram showing the top$-$level module and the two interacting trans$-$

mitter and receiver sub$-$modules. Clearly label all inputs and outputs for both the top$-$level

module and two sub$-$modules.

$6$b$.(7$ points$)$ Design a Mealy FSM for the receiver sub$-$module. Remember to consider all input.

signals for the receiver.

$6$c$.(7$ points$)$ Design a Mealy FSM for the transmitter module. Remember to consider all input

signals for the transmitter.