Question $6$

$6.(10$pts$)$ Draw the Register Transfer Level circuit for a $5-$stage Ring oscillator and write its Top$-$Level Structural Verilog description. Assume the inverter module has already been designed for you and has a module name of "inverter" which has input A and output O$.$

$//$ Predefined inverter module

module inverter $($input A$,$ output O$)$;

end module