Question $7[20$ Marks$]$

A researcher has developed a new type of nonvolatile memory, BossMem. He is considering BossMem as a replacement for DRAM. BossMein is $\backslash (10$ x $\backslash )$ faster $($all memory timings are $10$x faster$)$ than DRAM, but since BossMem is so fast, it has to frequently power$-$off to cool down. Overtheating is only a function of time, not a function of activity. An idle stick of BossMem has to power$-$off just as frequently DRAM and Bossick. When powered$-$off, BossMem retains its data, but can't service requests. Both finds that a system are banked and otherwise architecturally similar. To the researcher's dismay, he of BossMem.

a$)$ What can the researcher change or improve in the core $($he can't change BossMem or anything beyond the memory controller$)$ that will make his BossMem perform more favourably compared to DRAM, realizing that he will have to be fair and evaluate DRAM with his enhanced core as well?

b$)$ A colleague proposes to build a hybrid memory system, with both DRAM and BossMem. He decides to place data that exhibit low row buffer locality in DRAM and data that exhibits high row buffer locality in BossMem. Assume $\backslash (50\backslash \%\backslash )$ of requests are row buffer hits. Is this a good or bad idea? Briefly explain your answer.

c$)$ Now a colleague suggests trying to improve the last$-$level cache replacement policy in the system with the hybrid memory system. Like before, he wants to improve the performance of this system relative to one that uses just DRAM and he will have to be fair in his evaluation. Can he design a cache replacement policy that makes the hybrid memory system look more favorable? Justify NO or describe a cache replacement policy that would improve the performance of the hybrid memory system more than it would DRAM.

d$)$ Consider another nonvolatile memory technology, phase$-$change memory $($PCM$).$ Which technology between PCM$,$ BossMem, or DRAM requires the greatest attention to security? What is its vulnerability?

e$)$ Which is likely of least concem to a security researcher? Question $1[25$ Marks$]$

a$)$ Suppose you have $\backslash ($ N $\backslash )$ tasks and $\backslash (\backslash$boldsymbol$\{$P$\}\backslash )$ processors, where $\backslash ($ N$>\backslash$boldsymbol$\{$P$\}\backslash ).$ Discuss how you would assign tasks to processors statically $($fixed$)$ and dynamically $($adaptive$),$ also mention for both advantages and disadvantages.

b$)$ What is the difference between Instruction Level Parallelism, Data Parallelism and Task Level Parallelism? Also give the technology that is used in each.

c$)$ Explain how parallel task assignment can be implemented dynamically. Also mention the trade$-$offs between performing assignments using software and hardware.

d$)$ Propose an algorithm to implement task stealing mechanism in parallel task assignment systems.

Question $2[25]$

a$)$ Use Tomasulo's Algorithm to determine the number of clock cycles for the following:

b$)$ Consider an enhancement to the processor of a web server. The new CPU is $20$ times faster on search queries than the old processor. The old processor is busy with search queries $\backslash (70\backslash \%\backslash )$ of the time.

What is the speedup gained by integrating the enhanced CPU?

c$)$ You have just started work at NUL and your first task is to improve the overall performance of thuto. You find that memory operations currently take $\backslash (30\backslash \%\backslash )$ of execution time. You then decide to install a new processor which has a new widget called a "cache" that speeds up $\backslash (80\backslash \%\backslash )$ of memory operations by a factor of $4.$ Also, a second new widget called an $"$L$2$ cache" which speeds up $\backslash (1/2\backslash )$ the remaining $\backslash (20\backslash \%\backslash )$ by a factor of $2.$ What will be the total speed up$?$