QUESTION 8: VHDL CoDING- CoUNTERS (10 marks) The figure below is a simplified 74163 synchronous 4-bit counter with the following descriptions. All the changes of the Q outputs occur as a result of, and synchronous with, LOW to HIGH transition of clock (CLK) input If the clear input (CLR) is high, the counter resets to zero synchronously with CLK The input pin LOAD determines mode of the operation of this counter, if it is high data load synchronously from parallel inputs A, B, C, and D to the counter. If the LOAD is 0, the IC The counter increments when LOAD and CLR inputs are 0, with the clock transitions from . The counter outputs are available at QA to QD, where QA is LSB (least significant bit) and Qo is Write a behavioural level VHDL model for the counter. The USE area of the code is already given. works in count mode. LOW to HIGH. MSB (most significant bit) of the counter CLR LOAD_ CLK QB Qc QUESTION 8: VHDL CoDING- CoUNTERS (10 marks) The figure below is a simplified 74163 synchronous 4-bit counter with the following descriptions. All the changes of the Q outputs occur as a result of, and synchronous with, LOW to HIGH transition of clock (CLK) input If the clear input (CLR) is high, the counter resets to zero synchronously with CLK The input pin LOAD determines mode of the operation of this counter, if it is high data load synchronously from parallel inputs A, B, C, and D to the counter. If the LOAD is 0, the IC The counter increments when LOAD and CLR inputs are 0, with the clock transitions from . The counter outputs are available at QA to QD, where QA is LSB (least significant bit) and Qo is Write a behavioural level VHDL model for the counter. The USE area of the code is already given. works in count mode. LOW to HIGH. MSB (most significant bit) of the counter CLR LOAD_ CLK QB Qc