Question: Question II - Processor Design ( 4 0 min, / 5 0 ) This question deals with multicycle processor architectures. Some ISAs have support for

Question II - Processor Design (40 min, /50)
This question deals with multicycle processor architectures.
Some ISAs have support for memory instructions with post-increment. These
instructions perform both a load (or store) and an add to the address register.
The value added to the address register is the size of the operand loaded/stored.
For example:

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