Question Read the program carefully and you are asked to draw the single cycle architecture data path and control path for the following program. beq $s 1, $s2, L1 mul $s2, $s3 mflo $55 lw $s3,24 ($54) j exit LI: addi $s3, $s4, $s4 bgez $s3, L1 EXIT: Set the control signals properly to select the right inputs for ALU and right selection signals for MUXes used in the data path. Mem Mem Branch ALU Instru. Reg ction Dst ALU Src Mem Reg to Write Reg ALU Jump Read Write Opl BEQ MUL MFLO LW J ADDI BGEZ Question Read the program carefully and you are asked to draw the single cycle architecture data path and control path for the following program. beq $s 1, $s2, L1 mul $s2, $s3 mflo $55 lw $s3,24 ($54) j exit LI: addi $s3, $s4, $s4 bgez $s3, L1 EXIT: Set the control signals properly to select the right inputs for ALU and right selection signals for MUXes used in the data path. Mem Mem Branch ALU Instru. Reg ction Dst ALU Src Mem Reg to Write Reg ALU Jump Read Write Opl BEQ MUL MFLO LW J ADDI BGEZ