Question: Repeat problem 5.2 but apply to Figure 5.2.2. You need to take into account, the delays in the half adders blocks of the circuit. (assume operands Aand B as A = A6A5A0and B= B6B5B0)

5.2 For Figure 5.1.5, assume the gate delays in the circuit are 2 ns, 2 ns, and 3 ns for the AND, OR and XOR gates, respectively. Compute the delay in obtaining C1, C2, and C3, and C4. Similarly, compute the delays in obtaining S0, S1, S2 and S3. Generalize your answer to compute the delays, Cn and S(n -1), in terms of n.

below is figure 5.2.2

P3 A3 B3 B SUM CARRY S3 G3 PO P1 P2 GO c3 G1 G2 P2 A2 B2 SUM CARRY S2 G2 P1 A1 B1 SUM CARRY si G1 c1 PO SO AO BO SUM CARRY GO Figure 5.2.2: Design of a Carry-Lookahead Adder