Question:

Test Bench: Write VHDL code that generates the exhaustive set of input as shown in the

table below to simulate the D$-$Flip Flop

Important notes:

The submitted solution should include:

a$.$ The VHDL code as text for the test bench code and D$-$Flip Flop code,

additionally screenshots for your program

b$.$ Screenshot for every step during performing the simulation activity

c$.$ The wave that shows the final result