Question:

Test Bench: Write VHDL code that generates the exhaustive set of input as shown in the table below to simulate the D$-$Flip Flop

$\backslash$table$[[\frac{?}{\text{b}\text{a}\text{r}}(R),$Clk$,$D$,$Q$,$Qn$],[0,x,x,0,1],[1,0,x,$Last Q$,$Last Qn$],[1,1,x,$Last Q$,$Last Qn$],[1,f,0,0,1],[1,5,1,1,0]]$

Important notes:

The submitted solution should include:

a$.$ The VHDL code as text for the test bench code and D$-$Flip Flop code, additionally screenshots for your program

b$.$ Screenshot for every step during performing the simulation activity

c$.$ The wave that shows the final result