QUESTION3: Assume that initially cache holds x=150 in memory. Assume THREE processors use write invalidate protocol and complete the table given below show processor activity, bus activity and THREE processor cache data for each step. 4 Marks Bus Activity Processor Activity Contents of Contents of Contents of Contents in CPU A cache CPU B cache CPU C cache Memory location 150 CPU A reads Miss CPU Breads miss CPU C reads miss CPU B writes X=X+300 CPU A reads CPU C reads QUESTION3: Assume that initially cache holds x=150 in memory. Assume THREE processors use write invalidate protocol and complete the table given below show processor activity, bus activity and THREE processor cache data for each step. 4 Marks Bus Activity Processor Activity Contents of Contents of Contents of Contents in CPU A cache CPU B cache CPU C cache Memory location 150 CPU A reads Miss CPU Breads miss CPU C reads miss CPU B writes X=X+300 CPU A reads CPU C reads