Question5 A processor executes an instruction in the following five stages. Taken separately, the time required by each stage in picoseconds (1,000 ps 1 ns) is given for each stage. Page 3 of 4 IF instruction fetch (300ps) OF Operand fetch (250ps) OE Execute (350ps) MA Memory access (700ps) OS Operand store (write back) (200ps) (a) What is the total time required to execute an instruction if the processor is not pipelined? What is the rate of instructions completed per millisecond? (b) What is the total time required to execute an instruction assuming that this datapath is pipelined in five stages, and that a pipeline overhead of 20ps per stage is required in order to implement pipeline latches? Once this pipeline is full, what is the rate of instructions completed per millisecond? (c) Suppose that 25% of instructions are branch instructions, and half of the time a branch instruction causes a 3 cycle penalty (due to misprediction). What is the resulting average effective instruction execute time? what is the resulting instruction rate