quiqly

Question 5. Write a Verilog module for an ALU that has two signed n-bit inputs A[n1:0] and B[n1:C in 2's complement representation, where n is a parameter, and a 3-bit function F[2:0]. The ALU should produce as output an n-bit result R[n-1:0]. The ALU implements the following eight functions: Write a behavioral description in Verilog that uses an always block and procedural statements. For multiplication, use bit shifting and addition