Quiz\#3 Computer Organization and Design by P. Chen Spring 2023 1. According to the non-pipelined architecture shown below; (a) In addition to ALUOp, which control signals are required for lw, add, beq, and slt, respectively? List the values of them individually. (b) For add, the data path is PCIM Register FileALL Register File. What are the ones for the other 3 instructions'? 2. Transfonm 0.5 and 0.4375 into binary nommalized scientific notation, Perform addition and show all the details in 4 steps. 3. Consider the MIPS codes below, which are execuled in a 5-stage pipeline with forwarding. (a) Is there still any hazard? What kind? How many? Where? (b) Rearrange the instructions to avoid stalls. (c) Before and after the instruction scheduling, how many clock cycles are needed for this code segment? lw Stl, 0(St0) lw St2,4(St0) add $t3, St 1,$t2 sw $t3,12(St0) Iw Sl4,8(S10) add \$i5, St1, \$14 sw $15,16(St0)