Read the paper Amdahl's Law in the Multicore Era. Assume that the number of BCE (base...

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Read the paper "Amdahl's Law in the Multicore Era." Assume that the number of BCE (base core equivalent) is n=64. Assume two fractions of parallelism f1-0.98 and f2-0.90. Using the models described in the paper determine the Speedup for the following multicore configurations. For all questions assume that performance of an r-BCE core scales as perf(r)=(r)¹/² | (a) Symmetric multicore chip with 64 one BCE cores (64 x 1-bce). (b) Symmetric multicore chip with 16 four-BCE cores (16 x 4-bce). (c) Asymmetric multicore chip with one sixteen-BCE core and 48 single BCE cores (1 x 16-bce + 48 x 1-bce). (d) Dynamic multicore chip with one sixteen-BCE core and 48 single BCE cores. Which configuration does it give the highest speed for f1-0.98 and which one for f2=0.90? Why do not we assume that perf(r) = r? Explain your answer. Read the paper "Amdahl's Law in the Multicore Era." Assume that the number of BCE (base core equivalent) is n=64. Assume two fractions of parallelism f1-0.98 and f2-0.90. Using the models described in the paper determine the Speedup for the following multicore configurations. For all questions assume that performance of an r-BCE core scales as perf(r)=(r)¹/² | (a) Symmetric multicore chip with 64 one BCE cores (64 x 1-bce). (b) Symmetric multicore chip with 16 four-BCE cores (16 x 4-bce). (c) Asymmetric multicore chip with one sixteen-BCE core and 48 single BCE cores (1 x 16-bce + 48 x 1-bce). (d) Dynamic multicore chip with one sixteen-BCE core and 48 single BCE cores. Which configuration does it give the highest speed for f1-0.98 and which one for f2=0.90? Why do not we assume that perf(r) = r? Explain your answer.

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Solution a Symmetric multicore chip with 64 one BCE cores 64 x 1bce Speedup Speedup 1 f1 perfr f1 perfr 64 r Assuming perfr r2we can substitute and simplify Speedup 1 098 12 098 12 64 1 Speedup 002 29... View the full answer