Realize Verilog code to multiply an 8-bit input called data by a fixed constant, 11 and 15 respectively in decimal. Complete the following Verilog code, write a test bench

module multiply (data, product_11, product_15);

input [7:0] data ;

output [11:0] product_11 ;

output [11:0] product_15 ;

wire [11:0] product_11 ;

wire [11:0] product_15 ;

assign product_11 = ____________________; // 8 x data + 2 x data + data

assign product_15 = ____________________; // 8 x data + 4 x data + 2 x data + data

endmodule