Recall that the clock cycle time in a non$-$pipelined processor is determined by the instruction $($considering all stages$)$ that takes the longest time to execute as no instruction can take more than one cycle. In a pipelined datapath, the cycle time is determined by the individual stage that takes the longest time as each cycle will execute exactly one stage. Now assume the distribution of time required by independent stages are as follows:

IF ID EX MEM WB

$250350150300200$

Now answer the following questions:

a$)$ What should be the clock cycle time for a non$-$pipelined and a pipelined processor? Provide justification for your answer.

b$)$ How long will it take to execute the lw instruction in a non$-$pipelined processor? Why?

c$)$ How long will it take to execute the lw instruction in a pipelined processor? Why?