Reduced Instruction Set Computers

A reduced instruction set computer $($RISC$)$ is a type of microprocessor architecture that has applied the following architectural changes to the organization of a processor to improve its computing performance:

A RISC's instruction set only has a limited number of instructions.

A RISC's CPU accesses the memory and input$/$output $($I$/$O$)$ devices through separated data communication buses, which allows for more parallel computing. This is in contrast to a conventional processor architecture, where the CPU, memory, and I$/$O devices all share the same data communication bus.

A RISC's CPU can execute most instructions in one clock cycle.