Register (register-memory) Load R1,A Add R3,R1,B Store R3,C Stack Push A Push B Add Accumulator Load A Add B Store C Register (load-store) Load R1,A Load R2,B Add R3,R1,R2 Store R3,C Pop C Figure A.2 The code sequence for C A+Bfor four classes of instruction sets. Note that the Add instruction has implicit operands for stack and accumulator architectures and explicit operands for register architectures. It is assumed that A, B, and C all belong in memory and that the values of A and B cannot be destroyed. Figure A.1 shows the Add operation for each class of architecture. Register (register-memory) Load R1,A Add R3,R1,B Store R3,C Stack Push A Push B Add Accumulator Load A Add B Store C Register (load-store) Load R1,A Load R2,B Add R3,R1,R2 Store R3,C Pop C Figure A.2 The code sequence for C A+Bfor four classes of instruction sets. Note that the Add instruction has implicit operands for stack and accumulator architectures and explicit operands for register architectures. It is assumed that A, B, and C all belong in memory and that the values of A and B cannot be destroyed. Figure A.1 shows the Add operation for each class of architecture