Required to show simplified Boolean equation also. Thank you

Exercise 42 Sketch a schematic of the circuit described by the following H code. Simplify the schematic so that it shows a minimum number of lowing HDL gates. SystemVerilog module exercise2(input logic [3:0] a VHDL 1ibrary IEEE: use IEEE.STD LOGIC_1164.al1: entity exercise2 is output logic [1:0) y) port(a: in STD LOGIC VECTOR(3 downto 0): end: architecture synth of exercise2 is always.comb if (a[0])y=2'b1 1: else if (at1]) y 2'b10: else if (a(2]) y 2'b01: else if (a(3]) y 2'b00: else y: out STD LOGIC VECTORC1 downto 0)): begin endmodule process(all) begin if a(0) then y