Review the tutorial in Appendix B.3, Design Entry Using Schematic Capture" I. Perform the tutorial in Appendix B.4, Design Entry Using VHDL." Print out the simulation, but for your vhdl simulation use Zsss as the output variable where sss are the last three digits of one partner's student id number. Continue this approach of variable naming in all subsequent projects. Review the tutorial in Appendix B.3, Design Entry Using Schematic Capture" I. Perform the tutorial in Appendix B.4, Design Entry Using VHDL." Print out the simulation, but for your vhdl simulation use Zsss as the output variable where sss are the last three digits of one partner's student id number. Continue this approach of variable naming in all subsequent projects