Question: Ring counter Consider a datapath FSM with a four-bit state register state whose next state unction is described by the following Verilog statement: wire [3:

Ring counter Consider a datapath FSM with a four-bit state register state whose next state unction is described by the following Verilog statement: wire [3: 0] next = rest ? 0: {state [2: 0], ~state [3]}; Draw a state diagram for this FSM. Describe in plain English what function this FSM performs

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