RISC-V ASSEMBLY LANGUAGE

Problem 3 (30 points) Consider a pipeline architecture with perfect branch prediction (no stalls), with no delay slots, which has full forwarding support and which resolves branches in the EX (not ID) stage. This pipeline executes the code below: HERE ld x10, 0 (x13) ld x1l, 8 (x13) add x12, x10, x11 subi x13, x13, 16 beq x12, x0, HERE Kafter 2> Kafter 4> a) Assume the pipeline executes two iteration of the loop and show the pipeline execution diagram (graphical representation. Assume cc1 is HERE ld x10... instruction. During the two loop iterations which are the clock cycles for which the pipeline is full? Circle the stages that do not perform useful work (they just let partial results migrate from one b) c) pipeline register to the next)