Row Buffers:

For the following memory access pattern, estimate when each memory access completes for three different scheduling mechanisms: open-page policy, close-page policy, an oracular scheme that knows if another access to the same row is imminent. You are allowed to re-order requests already waiting in the memory controller. The access pattern only specifies the row being touched. All accesses are to the same bank. Assume that bus latencies are zero. Assume that the bank is already precharged at time 0. Assume that precharge takes 20 ns, loading a row buffer (Activate) takes 20 ns, and cache line transfer to output pins (Column-Rd) also takes 20 ns.

Row being accessed	Arrival time at memory controller	Open-Page	Close-Page	Oracular
X	20 ns
Y	70 ns
X	75 ns
Y	90 ns
X	210 ns
Y	260 ns